1. Field of the Invention
This invention relates to signal value storage circuitry.
2. Description of the Prior Art
It is known to provide signal value storage circuitry (e.g. transmission gate flip-flop (TGFF) circuitry) that is able to operate statically. Such static signal value storage circuitry is able to maintain a stored signal value when the clock signals are stopped. It is also known to provide dynamic signal value storage circuitry (e.g. true-single-phase-clock (TSPC) flip-flop circuitry), which is able to maintain a signal value while the clocks continue to be driven and typically operates faster, uses less power and requires fewer transistors than static signal value storage circuitry. A problem with static signal value storage circuitry is a requirement for more than one clock signal (e.g. a clock signal and an inverted form of this clock signal which together provide two-phase clocking), as this tends to increase power consumption and reduces clock robustness (e.g. vulnerability to clock skew). Dynamic signal value storage circuitry may be provided using a true single clock signal, but tends to be more vulnerable to variations in process/voltage/temperature which are becoming more significant as process geometries for integrated circuitry reduce in size and operating in voltages reduce. It is also desirable for the gate count of the storage circuitry to be low and that contention should not arise during operation of the storage circuitry.